This application is based upon and claims priority from prior French Patent Application No. 99-12406, filed Oct. 5, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to electronic devices, and more specifically to a semiconductor device such as a transistor that has a gate-all-around (GAA) gate architecture.
2. Description of Related Art
Semiconductor devices having a xe2x80x9cgate-all-aroundxe2x80x9d (GAA) gate architecture are particularly desired because of GAA""s extraordinary properties in terms of performance and the suppression of short-channel effects. These advantageous properties are due to the fact that in GAA architecture the thin silicon film constituting the channel of the device is surrounded by the gate and is exclusively controlled by the gate. Thus, the influence of the drain field is removed so the short-channel effects are eliminated. The volume inversion in the silicon film, or at least the effect of two parallel channels in thicker films, results in a very significant gain in performance for a given silicon area.
Such a GAA gate architecture is described in documents such as xe2x80x9cA new scaling methodology for the 0.1-0.025 xcexcm MOSFETxe2x80x9d by C. Fiegna, H. Iwai, T. Wada, T. Saito, E. Sangiorgi, and B. Ricco, Symp. VLSI Techn. Dig., 1993, pages 33-34; xe2x80x9cComparative Study of Advanced MOSFET Concepts,xe2x80x9d IEEE Trans. Electron Devices, Vol. 43, No. 10, 1996, pages 1742-1753; and xe2x80x9cDevice Design Considerations for Double-Gate, Ground-Plane and Single-Gated Ultra-Thin SOI MOSFETs at the 25 nm Channel Length Generation,xe2x80x9d Int, Electron Devices Meet. Tech. Dig., 1998, pages 407-410.
Despite the advantages afforded by the GAA gate architecture, a viable realization of a GAA device has not been achieved at the present time. Vertical GAA architecture structures, such as those described by T. Mizuno et al. (Symposium on VLSI Technology, 1998, pages 23-24) and M. Terauchi et al. (T. Electro Devices, December 1997, pages 2303-2305), come up against technological problems and the limitations imposed by the photolithographic etching steps. To benefit from a GAA architecture, very thin films on the order of 10 nm are required, which in terms of vertical orientation corresponds to the resolution of the photolithographic etching of the gate.
A horizontal orientation GAA structure has also been proposed, but the feasibility and the quality of epitaxy progressing in a tunnel made of dielectric material, as proposed by H-S. P. Wong et al. (UDM Techn. Digest, 1997, pages 427-430), do not appear to be reliable.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a simple and reliable process for fabricating a semiconductor device (e.g., a transistor) having a GAA gate architecture.
Another object of the present invention is to provide a process for fabricating a semiconductor device having a GAA gate architecture through a succession of simple steps that allow well-controlled, reproducible, and extremely thin (e.g., 1-20 nm) silicon (channel) layers to be produced.
Yet another object of the present invention is to provide a process for fabricating a semiconductor device having a GAA gate architecture in which the need for aggressive photolithography is eliminated.
A further object of the present invention is to provide a process for fabricating a semiconductor device having a GAA gate architecture in which low junction capacitances (junction on insulator) are realized.
Still another object of the present invention is to provide a gate-all-around semiconductor device with a substrate having an active central region made of semiconductor material surrounded by an insulating peripheral region made of dielectric material.
One embodiment of the present invention provides a method for fabricating a semiconductor device having a gate-all-around architecture. According to the method, a substrate is produced so as to include an active central region semiconductor material surrounded by an insulating peripheral region of dielectric material. The central region has an active main surface and the peripheral region has an insulating main surface. Further, the active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A first layer of monocrysta)ine Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the monocrystalbine silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure has side walls, an external surface, and an internal surface that defining a tunnel with a conesponding part of the active imain surface. A thin layer of a dielectric material that does not fill the tunnel is formed on the external and internal surfaces of the bridge structure and on the side walls. A conducting material is deposited so as to cover the bridge structure and fill the tunnel, and the conducting material is masked and etched in order to form a gate-all-around region for the semiconductor device. In a preferred method, selective epitaxy is used to form the first layer, non-selective epitaxy is used to form the silicon layer, and selective etching is used to remove the first layer.
Another embodiment of the present invention provides a semiconductor device that includes a substrate, a bridge structure on a main surface of the substrate, and a gate region. The substrate includes an active central region of semiconductor material surrounded by an insulating peripheral region of dielectric material, with the central region having an active main surface and the peripheral region having an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute the main surface of the substrate. Further, the bridge structure consists of silicon and has two opposed lateral polycrystalline parts that rest on opposed parts of the insulating peripheral region. The two opposed lateral polycrystalline parts are joined together by a thin central monocrystalline part that is spaced above the active region of the substrate, and the gate region surrounds at least a portion of the thin central part of the bridge structure. In one preferred embodiment, the thickness of the thin central monocrystalline part of the bridge is from 1 to 50 nm, and the thin central monocrystailine part is spaced from the main surface of the active central region of the substrate by a height of from 1 to 50 nm.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed deseption and specific examples, while indicating preferred embodiment of the present invention, are given by Way of illustration only and various modifications may naturally be performed without deviating from the present invention.